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Cypress Semiconductor /psoc63 /CPUSS /DP_STATUS

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Interpret as DP_STATUS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SWJ_CONNECTED)SWJ_CONNECTED 0 (SWJ_DEBUG_EN)SWJ_DEBUG_EN 0 (SWJ_JTAG_SEL)SWJ_JTAG_SEL

Description

Debug port status

Fields

SWJ_CONNECTED

Specifies if the SWJ debug port is connected; i.e. debug host interface is active: ‘0’: Not connected/not active. ‘1’: Connected/active.
SWJ_DEBUG_EN

Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is ‘1’ and thus debug clocks are on: ‘0’: Disabled. ‘1’: Enabled.
SWJ_JTAG_SEL

Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is ‘0’ (SWJ mode selected) and SWJ_CONNECTED is ‘1’ (SWJ is connected). ‘0’: SWD selected. ‘1’: JTAG selected.

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data